Field of the Invention
The present invention relates to an input buffer circuit, and more specifically, to an input buffer circuit of a semiconductor device inverting an output corresponding to a crossing point of complementary signals.
Description of the Background Art
The processing speed of a processing system such as a computer system or a communication system has been increasing recently, and the speed of Dynamic Random Access Memory (hereinafter referred to as DRAM) used as main memory in such processing system has been increasing as well. The Synchronous DRAM (hereinafter referred to as SDRAM) synchronizes, for example, with a clock signal that is a system clock, and receives an address signal and a control signal and performs data input/output. In SDRAM, it is not required to consider the margin for the skew of an external signal, and hence the internal operation can be performed at high speed.
Recently, the drastic improvement in operating speed of microprocessor (MPU) has been exceeding the improvement in operating speed of DRAM, and hence, in some cases access time and cycle time of DRAM may bottleneck the performance of overall system. Thus, in order to address high speed MPU, Double Data Rate SDRAM (hereinafter referred to as DDR SDRAM) has been proposed, which has double data rate as compared to SDRAM. In contrast to conventional SDRAM using only rising edge of a clock signal as a synchronizing signal, DDR SDRAM uses both of rising and falling edges of a clock signal as synchronizing signals. Further, it handles input/output signal of high frequency.
FIG. 8 is a circuit diagram showing the configuration of a conventional current mirror type input buffer circuit 100, as used for a semiconductor device such as DDR SDRAM.
As shown in FIG. 8, conventional current mirror type input buffer circuit 100 includes a P-channel MOS transistor 102 having gate drive voltage of input buffer circuit activation signal /EN and connected to power supply node 101 (voltage VDD), an N-channel MOS transistor 103 having gate drive voltage of input voltage DIN and having one end connected to ground node, an N-channel MOS transistor 104 having gate drive voltage of reference voltage VREF and having one end connected to ground node, a P-channel MOS transistor 105 connected between P-channel MOS transistor 102 and N-channel MOS transistor 104 and having gate drive voltage of the voltage of connection node N11 connecting to N-channel MOS transistor 104, a P-channel MOS transistor 106 connected between P-channel MOS transistor 102 and N-channel MOS transistor 103 and similarly having gate drive voltage of the voltage of connection node N11, and a buffer 110 connected to connection node N12 connecting P-channel MOS transistor 106 and N-channel MOS transistor 103.
P-channel MOS transistor 102 is rendered conductive when activation signal /EN is at L level to activate the input buffer circuit shown in FIG. 8, as well as to operate as a constant current source. Buffer 110 operates as a drive buffer that drives corresponding to the voltage of node N12.
Next, the operation of the current mirror type input buffer circuit will be described.
Here, it is assumed that proportion of W/L (W indicates channel width, and L indicates channel length) of P-channel MOS transistor 105 to W/L of N-channel MOS transistor 104 is the same with that of W/L of P-channel MOS transistor 106 to W/L of N-channel MOS transistor 103.
In this case, when input voltage DIN of the gate drive voltage of N-channel MOS transistor 103 is equal to reference voltage VREF of the gate drive voltage of N-channel MOS transistor 104, the voltage of node N12 will be xc2xd VDD. When input voltage DIN changes from reference voltage VREF, corresponding to that differential voltage, the voltage of node N12 changes from xc2xd VDD.
In other words, if input voltage DIN is higher than reference voltage VREF, then the voltage of node N12 will be lower than xc2xd VDD, and if input voltage DIN is lower than reference voltage VREF, then the voltage of node N12 will be higher than xc2xd VDD. Hence, by setting threshold value of buffer 110 to xc2xd VDD, reference voltage VREF will be the threshold voltage of input voltage DIN for the output of buffer 110.
Input buffer circuit 100 as described above and shown in FIG. 8 functions as a clock buffer circuit, which is one of the input buffer circuits, by inputting clock signal CK as reference voltage VREF, and clock signal /CK as input voltage DIN, respectively. This clock buffer circuit inverts the output corresponding to the crossing point of complementary clock signals CK, /CK.
FIG. 9 is a timing diagram related to the description of the operation of a semiconductor device such as DDR SDRAM.
Complementary clock signals CK, /CK are input to a clock buffer circuit such as described above referring to FIG. 8. The clock buffer circuit inverts the output corresponding to the crossing point of complementary clock signals CK, /CK. Command signal CMD generates READ command synchronizing to the output inversion. The semiconductor device internally performs a signal processing operation, and thereafter outputs data of data signal DQ to the outside of semiconductor device after time point t2. Thus, the semiconductor device such as DDR SDRAM initiates the internal operation synchronizing to the crossing point of complementary clock signals CK, /CK input to the clock buffer circuit.
Here, access time tAC is defined by the time difference from the crossing point of complementary clock signals CK, /CK to the time point data signal DQ crosses the level of reference voltage VREF (the signal level up to time point t2). For example, in FIG. 9, access time tAC is from time point t1 to t2, and from time points t3 to t4.
As for DDR 266, which is one product of DDR SDRAM, access time tAC is defined in the range of xe2x88x92750 psxe2x89xa6tACxe2x89xa6750 ps. In order to define access time tAC within this range, a delay process is performed inside DDR 266 to adjust the timing of the crossing point of complementary clock signals CK, /CK and data output of data signal DQ.
As in the foregoing, the semiconductor device such as DDR SDRAM initiates the internal operation synchronizing to the crossing point of complementary clock signals CK, /CK input to the clock buffer circuit, and access time tAC is affected by the initiation time of the internal operation. Complementary clock signals CK, /CK are assumed to cross with each other at the level of reference voltage VREF.
Complementary clock signals CK, /CK, however, do not always cross with each other at the level of reference voltage VREF, actually.
FIG. 10 is a timing diagram enlarging a portion where complementary clock signals CK, /CK cross with each other at the potential other than the level of reference voltage VREF.
As shown in FIG. 10, when complementary clock signals CK, /CK cross with each other at the potential other than the level of reference voltage VREF and if the clock buffer circuit is a current mirror type input buffer circuit, then response speed of output inversion changes corresponding to the potential level where clock signals cross with each other. As the speed of output inversion of the clock buffer circuit changes, the initiation time of the internal operation of the semiconductor device such as DDR SDRAM changes.
Since access time tAC is affected by the initiation time of the internal operation, when complementary clock signals CK, /CK cross with each other at the potential other than the level of reference voltage VREF, the value of access time tAC changes, as a result. In other words, if the clock buffer circuit is a current mirror type input buffer circuit, then access time tAC undesirably changes depending on the potential level at which complementary clock signals CK, /CK cross with each other.
The object of the present invention is to provide an input buffer circuit having constant response speed of output inversion irrespective of potential level at which complementary signals cross with each other.
The present invention is directed to an input buffer circuit inverting an output corresponding to a crossing point of complementary signals, which includes a first input buffer unit, a second input buffer unit, and a signal processing unit. The first input buffer unit includes a current mirror circuit and first and second transistors connected the current mirror circuit, and compares a voltage of an input signal input to gate terminal of the first transistor and a reference voltage input to gate terminal of the second transistor, and depending on the comparison result, provides a first output signal. The second input buffer unit includes identical circuit configuration to the first input buffer unit, and compares a voltage of the reference voltage input to gate terminal of a third transistor corresponding to the first transistor and a voltage of a signal, which is complementary to the input signal, input to gate terminal of a fourth transistor corresponding to the second transistor, and depending on the comparison result, provides a second output signal. The signal processing unit combines and buffers the first and second output signals and determines the logic of the input signal.
Therefore, according to the present invention, by combining two input buffer circuits and inputting complementary signals from opposing directions to each other, constant response speed of output inversion is attained, irrespective of potential level at which complementary signals cross with each other.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.